# d-Matrix Raptor AI accelerator development > Live situation record from CLSTR: https://clstr.news/situations/d-matrix-raptor-ai-accelerator-development > Updated: 2026-09-10T16:27:35.000Z. Sources: 6. Developments: 2. d-Matrix has introduced its Raptor accelerator, a new architecture designed to mitigate memory bandwidth bottlenecks in generative AI inference. The chip utilizes 3D-DRAM technology, stacking custom DRAM layers onto a TSMC N4 logic die via face-to-face bonding. This design aims to provide a balance between the high bandwidth of SRAM and the high capacity of HBM, achieving approximately 105 TB/s of memory bandwidth. The company claims the Raptor architecture offers roughly 20 times the bandwidth density per area compared to traditional methods and uses significantly less energy per gigabyte transferred than HBM4. The chip features 32 GB of 3D-DRAM capacity and is specifically intended to reduce latency and power consumption during the ‘decode’ phase of large language model workloads. Following the technical unveiling, d-Matrix announced plans to integrate Nvidia’s NVLink Fusion technology into its upcoming Raptor processors. This integration is intended to allow d-Matrix hardware to connect directly to Nvidia data-center systems. To support rapid data flow, the company is also partnering with Astera Labs. The Raptor processor is expected to complete its final design phase by the end of 2024, with compatible server racks scheduled for market release in 2027. ## Timeline ### 2026-09-10: d-Matrix to integrate Nvidia NVLink Fusion in AI inference chips AI startup d-Matrix will use Nvidia’s NVLink Fusion technology to integrate its Raptor processors directly into Nvidia data-center hardware for low-latency AI inference workloads by 2027. 2 sources. https://clstr.news/cluster/d-matrix-to-integrate-nvidia-nvlink-fusion-in-ai-inference-chips ### 2026-08-23: d-Matrix unveils Raptor accelerator with 105 TB/s 3D-DRAM bandwidth d-Matrix introduced its Raptor accelerator, using 3D-DRAM technology to achieve 105 TB/s bandwidth for generative AI inference, aiming to solve memory bottlenecks more efficiently than HBM. 4 sources. https://clstr.news/cluster/d-matrix-unveils-raptor-chip-using-3d-dram-for-ai-inference --- Cite as: d-Matrix Raptor AI accelerator development. CLSTR, https://clstr.news/situations/d-matrix-raptor-ai-accelerator-development