AI power delivery shifts toward 48V and vertical architectures

The rapid growth of AI computing is driving a fundamental redesign of power delivery architectures in data centers. As AI accelerators demand increasingly high currents—potentially exceeding 3000A—at very low voltages (below 0.8V), traditional power distribution methods are facing significant bottlenecks.

Industry experts and companies are shifting toward 48V power distribution networks (PDN) to reduce line losses and weight compared to traditional lower-voltage systems. A critical challenge is the ‘last inch’ of power delivery: the distance between the voltage regulator and the chip. To minimize power loss and impedance, there is a growing trend toward Vertical Power Delivery (VPD), which moves power components directly underneath the processor or integrates them into the chip package substrate.

Solutions being explored include Vicor’s Factorized Power Architecture (FPA), which separates voltage regulation from current multiplication to optimize placement, and proposals from startups like Saras Micro Devices to integrate passive components like inductors and capacitors directly into the processor package to improve efficiency and transient response.