AMD explores 3D DRAM to improve AI memory efficiency

AMD is exploring 3D DRAM technology as a potential successor to High Bandwidth Memory (HBM) to meet the growing energy and capacity demands of AI accelerators. During the Hot Chips 2026 event, industry leaders including AMD, Samsung, d-Matrix, and SK hynix presented approaches utilizing hybrid bonding.

This integration technique uses direct copper-to-copper connections instead of traditional microbumps or Through Silicon Vias (TSV) used in HBM stacks. AMD reports that 3D DRAM with hybrid bonding could be up to 17 times more energy-efficient than conventional HBM by reducing the energy required to transfer a single bit. By placing memory layers directly above or below the computing logic, the architecture minimizes signal distance and parasitic capacitance.

Despite the efficiency potential, significant manufacturing hurdles remain. The primary challenge is thermal management, as the high temperatures required during the wafer bonding process can negatively impact DRAM refresh rates and overall capacity. While HBM currently provides high bandwidth, it offers lower usable capacity per silicon wafer compared to traditional DRAM, driving the industry toward these three-dimensional alternatives.