AMD unveils 2nm Zen 6 EPYC ‘Venice’ servers with up to 256 cores for AI workloads

AMD announced that its next‑generation server processor family, codenamed “Venice,” will be built on TSMC’s N2 2 nm process and feature the new Zen 6 micro‑architecture. The first chips, EPYC Venice, are slated for launch at the Advancing AI 2026 event on 22 July and will support up to 256 CPU cores and 512 threads, a roughly 33 % increase over the current EPYC Turin generation. AMD projects up to 1.7 × performance improvement and memory bandwidth of up to 1.6 TB/s, with the processors intended for server and AI platforms alongside Instinct MI400 accelerators.

AMD’s senior vice‑president Dan McNamara explained that AI‑agent workflows require a range of compute profiles rather than a single CPU model. EPYC CPUs will be positioned for three key functions in agentic AI pipelines—orchestration, sandbox execution, and tool invocation—leveraging core density, high clock speeds, and large memory bandwidth. The upcoming Venice generation will raise core counts by 1.3 × and memory bandwidth by 2.5 ×, aiming to meet the diverse demands of enterprise AI workloads.