AMD unveils Physical AI strategy and Unified Memory architecture

At the Embedded Computing Summit (ECS) 2026 held in Tokyo, AMD detailed its strategy for the Physical AI market, which the company estimates will reach a total available market (TAM) of $200 billion by 2035.

AMD is addressing the latency issues inherent in traditional Physical AI solutions. Current architectures often rely on external NPUs or GPUs connected to MCUs or MPUs via interfaces like PCI Express or SPI. This creates significant communication overhead during the critical control loop of recognition, inference, decision, and action.

To mitigate this, AMD is introducing a Unified Memory architecture that integrates the NPU and CPU. This approach aims to reduce the time lost during data exchange between processors, providing the real-time control necessary for autonomous systems, such as advanced drones and other sensor-driven devices.