Cadence expands ChipStack AI with new RTL Generation Agent

Cadence Design Systems has expanded its ChipStack AI Super Agent by introducing an RTL Generation Agent. This new tool automates front-end digital design and verification tasks, allowing engineers to use natural-language prompts to convert high-level specifications into Register-Transfer Level (RTL) code.

The agent is designed to optimize designs based on power, performance, and area (PPA) targets. In early evaluations, the technology achieved an average area reduction of 24% and a power reduction of 18% compared to code generated solely by a foundation model, while maintaining 100% functional accuracy.

Honda R&D is currently evaluating the agent for use in automotive system-on-chip (SoC) designs. The collaboration aims to address the long development cycles of SoCs required for software-defined vehicles and autonomous driving, where safety and strict power and cost constraints are critical.