Cadence introduces Maestro AI model portfolio for semiconductor design

Cadence Design Systems has announced the Maestro AI Model Portfolio, a suite of AI models specifically designed to enhance semiconductor and electronic system design. By integrating specialized large language models, decision-making models, and self-improving AI agents with electronic design automation (EDA) and system design automation (SDA) tools, the company aims to address the increasing complexity of chip manufacturing.

Initial evaluations indicate that the Maestro portfolio can improve design quality by up to 30 percent and increase token utilization efficiency by up to five times compared to general-purpose foundation models. The system utilizes a closed-loop reinforcement learning mechanism, where design results are verified against engineering constraints and fed back into the models to improve future decision-making.

The Maestro portfolio powers four AI Super Agents: AuraStack, ChipStack, InnoStack, and ViraStack. Cadence is collaborating with NVIDIA to integrate NVIDIA’s Nemotron AI models and OpenShell security technology into this workflow. Early adopters include Socionext in Japan and Silicon Labs in the United States.