d-Matrix unveils Raptor accelerator with 105 TB/s 3D-DRAM bandwidth

d-Matrix has unveiled its Raptor accelerator, a new architecture designed to address memory bandwidth bottlenecks in generative AI inference. Utilizing 3D-DRAM technology, the chip stacks custom DRAM layers directly onto a TSMC N4 logic die using face-to-face bonding. This approach aims to provide a middle ground between the high bandwidth of SRAM and the high capacity of HBM.

According to technical data presented for Hot Chips 2026, the Raptor architecture can achieve approximately 105 TB/s of memory bandwidth. The company claims this provides roughly 20 times the bandwidth density per area compared to traditional approaches and uses 5 to 8 times less energy per gigabyte transferred than HBM4.

The Raptor chip features 32 GB of 3D-DRAM capacity across four packages. While HBM offers higher total capacity, d-Matrix asserts that Raptor’s design significantly reduces latency and power consumption by shortening the data path between the processor and memory, specifically targeting the ‘decode’ phase of large language model workloads.