ERS electronic launches automated panel-level packaging system for AI chips

ERS electronic GmbH has announced the launch of a fully automated panel-level packaging (PLP) system designed for 310x310 mm substrates. The new equipment integrates three thermally critical processes—temporary carrier bonding, debonding, and detaping—into a single automated platform. This integration aims to support AI and chiplet architectures by reducing the need to move panels between different machines, thereby minimizing transit time and the risk of substrate damage.

The system has a processing capacity of 13 panels per hour. According to the company, the first unit was delivered to a leading semiconductor manufacturer in September for integration into its production line. The technology is developed and manufactured at ERS’s facility in Barbing, Germany.

The shift toward 310x310 mm panels is driven by their superior area utilization compared to traditional 300 mm circular wafers. Industry projections from Yole Group suggest the panel-level packaging market will experience a compound annual growth rate exceeding 40% over the next five years, fueled by demand for 3D IC, HBM, and 2.5D IC packaging.