Huawei promotes LogicFolding chip technology amid thermal concerns

Huawei is promoting its LogicFolding technology, which utilizes vertical stacking of logic circuits to increase computing density as traditional process scaling faces limitations. By using high-density copper-to-copper hybrid bonding with micron-scale vertical interconnects, the architecture aims to shorten signal transmission paths. Huawei claims this can reduce typical core interconnect lengths by approximately 20%, with some critical paths shortened by up to 70%, potentially reducing the number of clock buffers by 50% and lowering power consumption.

However, semiconductor analysts have raised concerns regarding thermal management. Experts suggest that the vertical stacking creates heat dissipation challenges similar to Backside Power Delivery Network (BSPDN) technologies. This increased heat density could limit a chip's ability to maintain high clock speeds over extended periods. Consequently, analysts believe major mobile chipmakers like Qualcomm and Apple currently show limited interest in adopting LogicFolding for mobile SoCs, preferring to focus on advanced process node scaling. Some industry experts suggest it may take until around 2030 for Huawei's performance to rival advanced processes like TSMC's N3E.