IBM to release 0.7nm Nanostack design kits in early 2027

IBM has announced that its 0.7nm “Nanostack” process design kit (PDK) will be available to interested parties in the first quarter of 2027. This technology represents a shift from 2D to 3D transistor architectures by vertically stacking n-type and p-type transistors in an interleaved layout. This approach aims to optimize transistor density, performance, and power consumption.

A significant advantage of the Nanostack technology is its potential to address SRAM scaling issues. While traditional logic scaling faces challenges at smaller nodes, IBM’s 7-angstrom technology promises a 40% reduction in SRAM size. This is particularly critical for AI chips, where SRAM occupies a substantial portion of the die area.

In a related development, IBM is collaborating with Siemens to advance this architecture. The partnership combines IBM’s semiconductor innovation with Siemens’ expertise in electronic design automation (EDA), process simulation, and lithography optimization. The collaboration focuses on creating advanced virtual models to solve manufacturing challenges and accelerate the transition of Nanostack technology toward mass production.