IEEE launches AI processor architecture training program

IEEE Educational Activities, supported by the IEEE Computer Society, has launched a new five-course curriculum titled the ‘AI Processor Architecture, Design Principles, and Performance’ program. The initiative aims to address the increasing complexity in artificial intelligence hardware design, specifically targeting the ‘AI memory wall’—a performance bottleneck caused by the data transfer demands between memory and processors in large-scale neural networks.

The program is designed for hardware architects, chip designers, and embedded systems developers. It focuses on the industry shift toward domain-specific accelerator platforms and the necessity of joint hardware design and network-algorithm co-optimization.

The curriculum covers five core areas: • Fundamental principles of design and functionality • Practical insights into advanced architectures • Neural processing unit (NPU) deployment for industry • Emerging trends and evolving architectures • Design considerations for edge, cloud, quantum, and Internet of Things (IoT) environments.