Intel unveils XBM memory architecture to rival HBM4

Intel has disclosed a patent for a new ultra‑high‑bandwidth memory architecture called Cross‑Batch Memory (XBM). The design moves DRAM transistors to the back‑end‑of‑line metal layers (1T1C cells) and uses a serialized 32 GT/s UCIe interface instead of HBM's wide parallel bus. XBM can be built in 8‑ or 16‑layer stacks, keeping the same package footprint as HBM4 while aiming to cut packaging cost and improve yield through built‑in redundancy and self‑repair features. Intel plans to commercialise XBM after 2030, positioning it as a lower‑cost, high‑bandwidth alternative to HBM4 amid soaring AI‑chip demand and current HBM supply constraints. The company is also developing a separate Z‑Angle Memory (ZAM) technology, but XBM remains at the patent stage with no product roadmap announced.