Intel unveils XBM memory patent; server DRAM speeds reach DDR5‑8000 and beyond

Intel announced a new Cross‑Batch Memory (XBM) patent that relocates the charge‑control transistor to the back‑end‑of‑line metal layers, enabling a 3‑D stacked DRAM architecture that can compete with HBM4 at lower cost. The design supports 0.5 GB‑5 GB per chip, uses UCIe 32 GT/s interconnect, and targets commercialization around 2030 for AI data‑center servers, laptops and other devices.

At Computex, memory vendors showcased next‑generation server DRAM. Micron displayed DDR5‑8000 RDIMMs that double current DDR5‑6400 speeds while maintaining high capacity, and Samsung highlighted a second‑generation Multiplexed Rank DIMM (MRDIMM Gen2) aiming for 12 800 MT/s – a 45 % bandwidth increase over the current generation. These advances promise higher memory bandwidth per channel for upcoming x86 server platforms from Intel and AMD.