Qnity Electronics launches integrated platform for 3D semiconductor packaging

Qnity Electronics has launched a scalable materials and process technology platform designed to address the manufacturing complexities of next-generation 2.5D and 3D semiconductor packaging. The platform integrates four key technologies: metallization, bumping, dielectric materials, and fine-line patterning.

As the semiconductor industry shifts from traditional 2D designs toward complex vertical architectures—driven by advancements in Artificial Intelligence (AI), chiplets, high-bandwidth memory (HBM), and heterogeneous integration—manufacturers face increased demands for interconnect density and manufacturing yield. The Qnity platform aims to support advanced packaging methods such as Chip-on-Wafer-on-Substrate (CoWoS) and Embedded Multi-die Interconnect Bridge (EMIB).

Technical capabilities of the platform include support for SnAg micro-bumps, copper-to-copper direct and hybrid bonding, and high-resolution dielectric processes. The company reports that its metallization processes can achieve 2 µm line/space width while maintaining strict critical-dimension control and low defect rates. Additionally, the technology focuses on improving coplanarity and plating consistency, which are essential for fine-pitch applications and shrinking interconnect dimensions.