Qualcomm completes hardware verification for High Bandwidth Compute technology

Qualcomm has announced the successful hardware verification of its first-generation High Bandwidth Compute (HBC) technology at its San Diego laboratories. The technology verifies full read/write capabilities and near-memory computing functions.

HBC utilizes a vertical stacking architecture that places multiple layers of LPDDR memory directly above a computing chip. This design aims to increase memory bandwidth for AI inference while reducing power consumption by shortening the data transmission distance from centimeters to micrometers.

Qualcomm plans to sample the AI250 accelerator, which features this architecture, in the first half of 2027. The final product is expected to use a four-layer stack to provide 133 TB/s of effective bandwidth, representing an 18-fold increase over the AI200 accelerator. Early two-layer samples demonstrated a bandwidth-per-watt exceeding HBM4 by more than five times.

Industry partners including Samsung and SK Hynix have reportedly expressed interest in collaborating on the commercialization of HBC, with TSMC expected to handle the integration and packaging processes.