Samsung unveils zHBM concept for next-generation AI memory

zHBM AI memory 3D memory architecture HBM technology semiconductor innovation

At the Future of Memory and Storage (FMS) 2026 event in Santa Clara, California, Samsung Electronics unveiled its roadmap for next-generation AI memory architectures designed to enhance high-performance computing. A central highlight was the introduction of the zHBM concept model, which aims to stack High Bandwidth Memory (HBM) directly on top of AI accelerators (XPUs).

This vertical stacking approach seeks to minimize the physical connection distance between the memory and the processor, significantly reducing data transfer latency and power consumption compared to traditional HBM modules placed side-by-side on an interposer. Samsung estimates that zHBM could achieve a data transfer rate 4 to 8 times higher than HBM5, while reducing thermal resistance by up to 10 times.

Additionally, Samsung presented the V10 BV-NAND architecture, which utilizes new wafer bonding technology and features more than 400 layers. The company also introduced the zNAND-O concept model as part of its broader strategy to meet the rapidly increasing infrastructure demands of the AI revolution.