TIER IV to open-source AI chips for Level 4 autonomous driving

TIER IV has joined the Japan Science and Technology Agency (JST) ‘Next-Generation Edge AI Semiconductor Research and Development Project’ to develop a software-defined System-on-Chip (SoC) for Level 4 autonomous driving.

Working alongside Professor Hiroyuki Kawahara of the University of Tokyo, TIER IV will focus on the logical design of an AI chip optimized for efficient end-to-end (E2E) autonomous driving inference. A primary goal of the initiative is to open-source the design assets and the associated toolchain, including the compiler, to foster an open ecosystem.

The project aims to address the specific constraints of Level 4 autonomy, such as power efficiency, adaptability, transparency, and verifiability. By utilizing the Tensor Operator Set Architecture (TOSA) as a standardized intermediate representation, the team intends to decouple AI frameworks from hardware, allowing the system to adapt to evolving AI models through software updates rather than complete hardware redesigns. The resulting technology is intended to be compatible with the open-source Autoware platform.