TSMC A16 Backside Power Technology Adopted for NVIDIA Rosa CPUs

TSMC unveiled its A16 process at the IEEE/JSAP VLSI 2026 symposium, highlighting the Super Power Rail (SPR) backside power‑delivery scheme. The technology moves the primary power network to the wafer’s backside, freeing front‑side metal for signal routing and reducing IR drop. TSMC claims SPR delivers 8‑10% higher speed at equal power, 15‑20% lower power at equal speed, and about a 10% increase in chip density, with mass production slated for the fourth quarter of 2026.

NVIDIA’s upcoming Rosa CPUs, expected in 2029, are reported to be targeting TSMC’s most advanced nodes—either the 2 nm family or the A16 process with SPR. By using backside power delivery, Rosa aims to boost single‑thread performance for AI and high‑performance‑computing workloads while keeping power consumption low. The adoption would also raise demand for related semiconductor manufacturing steps such as chemical‑mechanical polishing and carrier wafers in Taiwan’s supply chain.