TSMC mass-produces 5.5x reticle size CoWoS packaging

TSMC Vice President of Advanced Packaging, He Jun, announced that the company has entered mass production of 5.5x reticle size CoWoS (Chip on Wafer on Substrate) technology. The process has demonstrated high stability, with yields exceeding 98% and reaching up to 99% for certain AI customer products.

Looking ahead, TSMC aims to expand CoWoS to 14x or 15x reticle sizes by 2029. The company is also advancing its SoIC hybrid bonding technology, targeting a 4.5-micrometer bonding pitch by 2029 to enable high-density 3D stacking.

He Jun identified ABF (Ajinomoto Build-up Film) substrates as the next critical bottleneck in the AI packaging supply chain, following memory. He noted that while customers are using multi-source procurement strategies to secure substrates, differences in thermal expansion and mechanical properties between suppliers can complicate system-level integration and yield management.

To address these complexities, TSMC is shifting toward System-Technology Co-Optimization (STCO). This approach integrates chip, package, substrate, PCB, and thermal design early in the development process to mitigate issues like die-edge damage that only appear during system-level integration.