Glass substrate technology advances for AI chip packaging

The semiconductor industry is seeing renewed interest in glass core substrates to meet the demands of large-scale, high-performance AI chip packaging. Glass offers superior rigidity and thermal stability compared to traditional organic substrates, which face warpage issues as package sizes increase.

Japanese firm Shinko Electric Industries has developed a 22-layer glass substrate featuring 11 copper wiring layers on each side. To address internal cracking and delamination, known as the “SeWaRe” issue, the company utilizes resin-reinforced edges and specialized edge-protection materials to disperse stress. Additionally, DNP has launched a through-glass via (TGV) pilot line in Saitama, targeting mass production by 2028.

In South Korea, Samsung Electro-Mechanics is working to close the technological gap through its GlaSSEM joint venture with Dongwoo Fine-Chem. Meanwhile, Taiwan-based Asia Intelligence Technology reports that while the industry is currently in the R&D and pilot line stages, the 510x515mm dimension is likely to become the mainstream standard for mass production. This size would allow manufacturers to adapt existing IC substrate equipment, thereby reducing capital expenditure.