Micron announces DRAM scaling strategy and NAND roadmap

Micron has announced its strategic direction for memory technology, opting to bypass the 4F² DRAM architecture in favor of continued scaling of existing designs and a transition to 3D DRAM. During a recent technology webinar, Chief Technology and Products Officer Scott DeBoer stated that while the company has investigated the 4F² approach for two decades, the added complexity and cost do not offer a viable scaling path. DeBoer noted that capacitor pitch, rather than cell size alone, remains the defining factor for DRAM.

In its NAND roadmap, Micron is accelerating its development by skipping a generation to move from Gen 9 to Gen 11 technology. This Gen 11 3D-NAND, which utilizes wafer-on-wafer bonding technology, is expected to ramp up in the second half of next year. The new generation aims to provide twice the bit density, a 1.5x increase in I/O speed, and a 25 percent reduction in energy consumption per bit compared to previous generations. Micron expects to exceed 400 layers with this technology.